1. Technical Field
The present disclosure is directed to a flip chip device having simplified routing demands, and more particularly, to a die having a first plurality of bump pads between a die seal and a plurality of input/output contact pads.
2. Description of the Related Art
FIG. 1 is a first die 20 having a plurality of solder bumps 22 formed in an array 24 within an internal edge 25 of a plurality of contact pads 26 in a known flip-chip design. Flip chip is a method of electrically connecting the first die 20 to a package carrier, which is either a substrate or a lead frame. This method addresses problems that arise from higher integration density and rising power consumption. Flip chip is particularly beneficial for high speed applications and has the following advantages: reduced signal inductance, reduced power and ground inductance, reduced package footprint, smaller die size, shorter wire lengths, higher signal density, and lower thermal effects.
The first die 20 has a chip outline boundary 28 that is spaced from an external edge 30 of the contact pads 26 by an area 32. The chip outline boundary 28 is formed when the first die 20 is separated from adjacent die on a wafer (not shown). The area 32 from the chip outline boundary 28 to the external edge 30 is between 100 and 150 microns. This area 32 contains test structures and mechanical support structures that prevent the functional circuits and the contact pads 26 from being damaged when the die are separated. The area 32 does not include any operational circuit structures and is considered wasted space.
The first die 20 is 6860 microns by 7100 microns and includes 9 rows of solder bumps 22 extending inward from each internal edge 25. The solder bumps 22 of the array 24 are spaced at the absolute minimum spacing in order to have these desired dimensions. All of the solder bumps 22 are formed within the interior edge 25 of the contact pads 26. Routing is challenging with this flip chip arrangement especially at the corners, where there are 81 solder pads 22 tightly packed together. In particular, routing lines (see FIG. 2) for power and ground solder pads face issues when formed too close together. The density of the solder pads 22 at the corners is problematic, causing signal quality issues.
FIG. 2 is an enhanced view of a known arrangement of a plurality of routing lines 40 coupling a plurality of solder bumps 42 to a plurality of contact pads 44 in a second die 46. Although not identical to the solder bump arrangement of FIG. 1, both the first and the second die, 20, 46 have routing challenges in corners, such as corner 48. To address the routing issues in the corner, the second die reduces the number of solder bumps 42 as compared to the solder bumps 22 of the first die 20.
In order to avoid cross-talk or other noise, the routing lines 40 are painstakingly designed to adequately connect the interior most solder bumps 42 to the contact pads 44 in the corner 48. For example, a first solder bump 42a is coupled to a first contact pad 44a through an intricate routing pattern 40a and through a second solder bump 42b. The routing lines 40 are formed in a redistribution layer, which may be formed on a top or a bottom side of the die 46.
In addition, to achieve high speed performance a length of the routing lines must be precise and shorter distances are preferred. If there are more than two rows of active or signal carrying bump pads, the routing pitch becomes an issue. Ensuring that the routing lines can get to internal bumps without signal degradation becomes challenging, especially for high speed bus requirements with tight timing specifications that require that all routing lines heading to the internal bumps to be the same length. As the routing line length increases, the risk of voltage drop also increases. A way to address the voltage drop is to make the routing lines wider, however, this is limited by the minimum spacing of the bump pads unless the overall dimension of the die are increased.